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acpl-7970 optically isolated sigma-delta modulator data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the acpl-7970 is a 1-bit, second-order sigma-delta ( - ? ) modulator converts an analog input signal into a high- speed data stream with galvanic isolation based on optical coupling technology. the acpl-7970 operates from a 5 v power supply with dynamic range of 78 db with an appro - priate digital flter. the diferential inputs of 200 mv (full scale 320 mv) are ideal for direct connection to shunt resistors or other low-level signal sources in applications such as motor phase current measurement. the analog input is continuously sampled by a means of sigma-delta over-sampling using an on-board clock. the signal information is contained in the modulator data, as a density of ones with data rate of 10 mhz, and the data are encoded and transmitted across the isolation boundary where they are recovered and decoded into high-speed data stream of digital ones and zeros. the original signal information can be reconstructed with a digital flter. the serial interface for data and clock has a wide supply range of 3 v to 5.5 v. combined with superior optical coupling technology, the modulator delivers high noise margins and excellent immunity against isolation-mode transients. with 0.5 mm minimum distance through insulation (dti), the acpl -7970 provides reliable reinforced insulation and high working insulation voltage, which is suitable for fail-safe designs. this outstanding isolation performance is superior to alternatives including devices based on capacitive- or magnetic-coupling with dti in micro-meter range. ofered in a dip-8 package, the isolated adc delivers the reliabil - ity, small size, superior isolation and over-temperature performance motor drive designers need to accurately measure current at much lower price compared to tradi - tional current transducers. the external clock version modulator acpl-796j (so-16 package) is also available. features ? 10 mhz internal clock ? 1-bit, second-order sigma-delta modulator ? 16 bits resolution no missing codes (12 bits enob) ? 78 db snr ? 6 m v/c maximum ofset drift ? 1% maximum gain error ? internal reference voltage ? 200 mv linear range with single 5 v supply ( 320 mv full scale) ? 3 v to 5.5 v wide supply range for digital interface ? -40 c to +105 c operating temperature range ? 25 kv/ m s common-mode transient immunity ? safety and regulatory approvals: C iec/en/din en 60747-5-5: 891 vpeak working insulation voltage C ul 1577: 5000 vrms/1min isolation voltage C csa: component acceptance notice #5 applications ? motor phase and rail current sensing ? power inverter current and voltage sensing ? industrial process control ? data acquisition systems ? general purpose current and voltage sensing ? traditional current transducer replacements functional block diagram -? modulator/ encoder v in+ shield v in? buf v ref led driver clk decoder gnd1 v dd1 mdat mclk v dd2 gnd2
2 pin confguration and descriptions figure 1. pin confguration. v dd1 1 2 3 4 8 7 6 5 v in+ v in? gnd1 v dd2 mclk mdat gnd2 acpl-7970 table 1. pin descriptions. pin no. symbol description 1 v dd1 supply voltage for signal input side (analog side), relative to gnd1 2 v in + positive analog input, recommended input range 200 mv 3 v in C negative analog input, recommended input range 200 mv (normally connected to gnd1) 4 gnd1 supply ground for signal input side 5 gnd2 supply ground for data/clock output side (digital side) 6 mdat modulator data output 7 mclk modulator clock output 8 v dd2 supply voltage for data output side, relative to gnd2 table 2. ordering information acpl-7970 is ul recognized with 5000 vrms/1 minute rating per ul 1577. part number option (rohs compliant) package surface mount gull wing tape & reel iec/en/din en 60747-5-5 quantity acpl-7970 -000e 300 mil dip-8 x 50 per tube -300e x x x 50 per tube -500e x x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example: acpl-7970-500e to order product of surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval and rohs compliance. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 package outline drawings standard dip package 1.78 (0.070) max. 1.19 (0.047) max. a 7970 yyww date code 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). note: floating lead protrusion is 0.5 mm (20 mils) max. 5 6 7 8 4 3 2 1 5? typ. 0.20 (0.008) 0.33 (0.013) 6.35 0.25 (0.250 0.010) 7.62 0.25 (0.300 0.010) 9.80 0.25 (0.386 0.010) 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) note: initial or continued variation in the color of the white mold compound is normal and does not afect device performance or reliability. figure 2.
4 gull wing surface mount option 300 dimensions in millimeters (inches). tolerances (unless otherwise speci?ed): xx.xx = 0.01 lead coplanarity xx.xxx = 0.005 maximum: 0.102 (0.004) note: foating lead protrusion is 0.5 mm (20 mils) max. 5 6 7 8 4 3 2 1 a 7970 yyww 6.350 0.25 (0.025 0.010) 9.80 0.25 (0.386 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc 12 nom. 0.20 (0.008) 0.33 (0.013) 0.635 0.25 (0.025 0.010) 7.62 0.25 (0.300 0.010) 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) figure 3. regulatory information the acpl-7970 is approved by the following organizations: iec/en/din en 60747-5-5 approved with maximum working insulation voltage v iorm = 891 vpeak. ul approval under ul 1577, component recognition program up to v iso = 5000 vrms/1min. file e55361. csa approval under csa component acceptance notice #5, file ca 88324. recommended pb-free ir profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used.
5 table 3. iec/en/din en 60747-5-5 insulation characteristics [1] description symbol value units installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms for rated mains voltage 450 v rms for rated mains voltage 600 vrms i-iv i-iv i-iv i-iv climatic classifcation 55/105/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 891 vpeak input to output test voltage, method b v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 1671 vpeak input to output test voltage, method a v iorm x 1.6 = v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc v pr 1426 vpeak highest allowable overvoltage (transient overvoltage, t ini = 60 sec) v iotm 8000 vpeak safety-limiting values (maximum values allowed in the event of a failure) case temperature input current [2] output power [2] t s i s,input p s,output 175 400 600 c ma mw insulation resistance at t s , v io = 500 v r s f 10 9 notes: 1. insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the application. 2. safety-limiting parameters are dependent on ambient temperature. the input current, i s,input , derates linearly above 25 c free-air temperature at a rate of 2.67 ma/c; the output power, p s,output , derates linearly above 25 c free-air temperature at a rate of 4 mw/c. table 4. insulation and safety related specifcations parameter symbol value units conditions minimum external air gap (external clearance) l(101) 7.4 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (external creepage) l(102) 8.0 mm measured from input terminals to output terminals, shortest distance path along body minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
6 table 5. absolute maximum ratings parameter symbol min. max. units storage temperature t s -55 +125 c ambient operating temperature t a -40 +105 c supply voltage v dd1 , v dd2 -0.5 6.0 v steady-state input voltage [1, 3] v in+ , v inC -2 v dd1 + 0.5 v two-second transient input voltage [2] v in+ , v inC -6 v dd1 + 0.5 v digital output voltages mclk, mdat -0.5 v dd2 + 0.5 v lead solder temperature 260 c for 10 sec., 1.6 mm below seating plane notes: 1. dc voltage of up to -2 v on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions. 2. transient voltage of 2 seconds up to -6 v on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions. 3. absolute maximum dc current on the inputs = 100 ma, no latch-up or device damage occurs. table 6. recommended operating conditions parameter symbol min. max. units ambient operating temperature t a -40 +105 c v dd1 supply voltage v dd1 4.5 5.5 v v dd2 supply voltage v dd2 3 5.5 v input voltage range [1] v in+ , v inC -200 +200 mv notes: 1. full scale input range 320 mv.
7 table 7. electrical specifcations unless otherwise noted, t a = -40 c to +105 c, v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v, v in + = -200 mv to +200 mv, and v in C = 0 v (single-ended connection); tested with sinc 3 flter, 256 decimation ratio. parameter symbol min. typ. [1] max. units test conditions/notes fig. static characteristics resolution 16 bits decimation flter output set to 16 bits integral nonlinearity inl -1 5 3 1 5 lsb t a = -40 c to +85 c; see defnitions section - 25 3 25 lsb t a = 85 c to 105 c diferential nonlinearity dnl - 0.9 0.9 lsb no missing codes, guaranteed by design; see defnitions section ofset error v os -2 0.4 2 mv t a = -40 c to +105 c; see defnitions section 5 ofset drift vs. temperature tcv os 2 6 m v/c v dd1 = 5 v ofset drift vs. v dd1 220 m v/v internal reference voltage v ref 320 mv reference voltage tolerance g e -1 1 % t a = 25 c, v in + = - 320 to + 320 mv; see defnitions section -2 2 % t a = -40 c to +105 c, v in + = - 320 to + 320 mv 6 v ref drift vs. temperature tcg e 60 ppm/c v ref drift vs. v dd1 -1.3 mv/v note 4 analog inputs full-scale diferential voltage input range fsr 320 mv v in = v in + C v in C; note 2 average input bias current i ina -0.3 m a v dd1 = 5v, v dd2 = 5v, v in + = 0 v; note 3 7 average input resistance r in 24 k across v in + or v in C to gnd1; note 3 input capacitance c ina 8 pf across v in + or v in C to gnd1 dynamic characteristics v in + = 400 mvpp, 1 khz sine wave signal-to-noise ratio snr 68 78 db t a = -40 c to +105 c; see defnitions section 8 signal-to-(noise + distortion) ratio sndr 65 75 db t a = -40 c to +105 c; see defnitions section 9 efective number of bits enob 12 bits see defnitions section isolation transient immunity cmr 25 kv/ m s v cm = 1 kv; see defnitions section common-mode rejection ratio cmrr 74 db digital outputs output high voltage v oh v dd2 C 0.2 v dd2 C 0.1 v i out = -200 m a output low voltage v ol 0.6 v i out = +1.6 ma power supply v dd1 supply current i dd1 9 14 ma v in + = C320 mv to +320 mv 10 v dd2 supply current i dd2 5.2 8 ma v dd2 = 5 v supply 11 4.6 7 ma v dd2 = 3.3 v supply 12 notes: 1. all typical values are at t a = 25 c, v dd1 = 5 v, v dd2 = 5 v. 2. beyond the full-scale input range the data output is either all zeroes or all ones. 3. because of the switched-capacitor nature of the isolated modulator, time averaged values are shown. 4. v ref drift vs. v dd1 can be expressed as C0.4%/v with reference to v ref .
8 table 8. timing specifcations unless otherwise noted, t a = -40 c to +105 c, v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v. parameter symbol min. typ. max. units test conditions/notes fig. modulator clock output frequency f mclk 9 10 11 mhz clock duty cycle 40% to 60% 13 data access time after mclk rising edge t a 40 ns c l = 15 pf 4 data hold time after mclk rising edge t h 10 ns c l = 15 pf 4 figure 4. data timing. table 9. package characteristics parameter symbol min. typ. max. unit test condition note input-output momentary withstand voltage v iso 5000 vrms rh < 50%, t = 1 min; t a = 25 c 1, 2 input-output resistance r i-o 10 12 10 13 v i-o = 500 v dc 3 10 11 t a = 100 c 3 input-output capacitance c i-o 1.4 pf f = 1 mhz 3 notes: 1. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage f 6000 vrms for 1 second (leakage detection current limit, i i-o 5 m a). this test is performed before the 100% production test for partial discharge (method b) shown in iec/en/din en 60747- 5-5 insulation characteristic table. 2. the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating, refer to the iec/en/din en 60747-5-5 insulation characteristics table and your equipment level safety specifcation. 3. this is a two-terminal measurement: pins 1C4 are shorted together and pins 5C8 are shorted together. t a mc lk mda t t h
9 typical performance plots unless otherwise noted, t a = 25 c, v dd1 = 5 v, v dd2 = 5 v, v in + = C200 mv to +200 mv, and v in C = 0 v, with sinc 3 flter, 256 decimation ratio. figure 5. ofset change vs. temperature. figure 6. v ref change vs. temperature figure 7. input current vs. input voltage. figure 8. snr vs. temperature. figure 9. sndr vs. temperature. figure 10. i dd1 vs. v in dc input at various temperatures. -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) v os (mv) 305 310 315 320 325 330 335 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) v ref (mv) -30 -20 -10 0 10 20 30 -400 -320 -240 -160 -80 0 80 160 240 320 400 v in + (mv) i in + (a) 66 68 70 72 74 76 78 80 82 84 86 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) snr (db) 66 68 70 72 74 76 78 80 82 84 86 -55 -35 -15 5 25 45 65 85 105 125 temperature (c) sndr (db) 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 -400 -300 -200 -100 0 100 200 300 400 v in (mv) i dd1 (ma) 25 c -40 c 105 c
10 figure 13. clock frequency vs. temperature for various v dd1 . figure 11. i dd2 (v dd2 = 5 v) vs. v in dc input at various temperatures. figure 12. i dd2 (v dd2 = 3.3v) vs. v in dc input at various temperatures. 2.0 3.0 4.0 5.0 6.0 7.0 8.0 -400 -300 -200 -100 0 100 200 300 400 v in (mv) i dd2 (ma) 25 c -40 c 105 c v dd2 = 5 v 2.0 3.0 4.0 5.0 6.0 7.0 8.0 -400 -300 -200 -100 0 100 200 300 400 25c -40c 105c v in (mv) i dd2 (ma) 9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5 -55 -35 -15 5 25 45 65 85 105 125 4.5v 5v 5.5v temperature (c) clock frequency (mhz) v dd2 = 3.3 v
11 defnitions integral nonlinearity (inl) inl is the maximum deviation of a transfer curve from a straight line passing through the endpoints of the adc transfer function, with ofset and gain errors adjusted out. diferential nonlinearity (dnl) dnl is the deviation of an actual code width from the ideal value of 1 lsb between any two adjacent codes in the adc transfer curve. dnl is a critical specifcation in closed-loop applications. a dnl error of less than 1 lsb guarantees no missing codes and a monotonic transfer function. ofset error ofset error is the deviation of the actual input voltage corresponding to the mid-scale code (32,768 for a 16-bit system with an unsigned decimation flter) from 0 v. ofset error can be corrected by software or hardware. gain error (full-scale error) gain error includes positive full-scale gain error and negative full-scale gain error. positive full-scale gain error is the deviation of the actual input voltage correspond - ing to positive full-scale code (65,535 for a 16-bit system) from the ideal diferential input voltage (v in + C v in C = +320 mv), with ofset error adjusted out. negative full- scale gain error is the deviation of the actual input voltage corresponding to negative full-scale code (0 for a 16-bit system) from the ideal diferential input voltage (v in + C v in C = -320 mv), with ofset error adjusted out. gain error includes reference error. gain error can be corrected by software or hardware. signal-to-noise ratio (snr) the snr is the measured ratio of ac signal power to noise power below half of the sampling frequency. the noise power excludes harmonic signals and dc. signal-to-(noise + distortion) ratio (sndr) the sndr is the measured ratio of ac signal power to noise plus distortion power at the output of the adc. the signal power is the rms amplitude of the fundamental input signal. noise plus distortion power is the rms sum of all non-fundamental signals up to half the sampling frequency (excluding dc). efective number of bits (enob) the enob determines the efective resolution of an adc, expressed in bits, defned by enob = (sndr ? 1.76)/6.02 isolation transient immunity (cmr) the isolation transient immunity (also known as common- mode rejection or cmr) specifes the minimum rate-of- rise/fall of a common-mode signal applied across the isolation boundary beyond which the modulator clock or data is corrupted. product overview description the acpl-7970 isolated sigma-delta ( - ? ) modulator converts an analog input signal into a high-speed (10 mhz typical) single-bit data stream by means of a sigma- delta over-sampling modulator. the time average of the modulator data is directly proportional to the input signal voltage. the modulator uses internal clock of 10 mhz. the modulator data are encoded and transmitted across the isolation boundary where they are recovered and decoded into high-speed data stream of digital ones and zeros. the original signal information is represented by the density of ones in the data output. the other main function of the modulator (optocoupler) is to provide galvanic isolation between the analog signal input and the digital data output. it provides high noise margins and excellent immunity against isolation-mode transients that allows direct measurement of low-level signals in highly noisy environments, for example mea - surement of motor phase currents in power inverters. with 0.5 mm minimum dti, the acpl-7970 provides reliable double protection and high working insulation voltage, which is suitable for fail-safe designs. this out - standing isolation performance is superior to alternatives including devices based on capacitive- or magnetic- coupling with dti in micro-meter range. ofered in an dip-8 package, the isolated adc delivers the reliability, small size, superior isolation and over-temperature perfor - mance motor drive designers need to accurately measure current at much lower price compared to traditional current transducers.
12 analog input the diferential analog inputs of the acpl-7970 are im - plemented with a fully-diferential, switched-capacitor circuit. the acpl-7970 accepts signal of 200 mv (full scale 320 mv), which is ideal for direct connection to shunt based current sensing or other low-level signal sources applications such as motor phase current mea - surement. an internal voltage reference determines the full-scale analog input range of the modulator (320 mv); an input range of 200 mv is recommended to achieve optimal performance. users are able to use higher input range, for example 250 mv, as long as within full-scale range, for purpose of over-current or overload detection. figure 14 shows the simplifed equivalent circuit of the analog input. in the typical application circuit (figure 19), the acpl-7970 is connected in a single-ended input mode. given the fully diferential input structure, a diferential input con - nection method (balanced input mode as shown in figure 15) is recommended to achieve better performance. the input currents created by the switching actions on both of the pins are balanced on the flter resistors and cancelled out each other. any noise induced on one pin will be coupled to the other pin by the capacitor c and creates only common mode noise which is rejected by the device. typical values for ra (= rb) and c are 22 and 10 nf re - spectively. latch-up consideration latch-up risk of cmos devices needs careful consider - ation, especially in applications with direct connection to signal source that is subject to frequent transient noise. the analog input structure of the acpl-7970 is designed to be resilient to transients and surges, which are often encountered in highly noisy application environments such as motor drive and other power inverter systems. other situations could cause transient voltages to the inputs include short circuit and overload conditions. the acpl-7970 is tested with dc voltage of up to -2 v and 2-second transient voltage of up to -6 v to the analog inputs with no latch-up or damage to the device. modulator data output input signal information is contained in the modulator output data stream, represented by the density of ones and zeros. the density of ones is proportional to the input signal voltage, as shown in figure 16. a diferential input signal of 0 v ideally produces a data stream of ones and zeros in equal densities. a diferential input of -200 mv corresponds to 18.75% density of ones, and a diferen - tial input of +200 mv is represented by 81.25% density of ones in the data stream. a diferential input of +320 mv or higher results in ideally all ones in the data stream, while input of -320 mv or lower will result in all zeros ideally. table 5 shows this relationship. figure 14. analog input equivalent circuit. figure 15. simplifed diferential input connection diagram. 200 ? (typ) 3 pf (typ) 3 pf (typ) f switch = mclk v in+ v in? 200 ? (typ) 1.5 pf 1.5 pf common mode voltage f switch = mclk analog ground acpl-7970 5 v +analog input ?analog input ra rb c v in+ v in? v dd1 gnd1 ?fs (analog input) +fs (analog input) 0 v (analog input) time modulator output analog input figure 16. modulator output vs. analog input.
13 table 10. input voltage with ideal corresponding density of 1s at modulator data output, and adc code. analog input voltage input density of 1s adc code (16-bit unsigned decimation) full-scale range 640 mv +full-scale +320 mv 100% 65,535 +recommended input range +200 mv 81.25% 53,248 zero 0 mv 50% 32,768 Crecommended input range -200 mv 18.75% 12,288 Cfull-scale -320 mv 0% 0 notes: 1. with bipolar ofset binary coding scheme, the digital code begins with digital 0 at Cfs input and increases proportionally to the analog input until the full-scale code is reached at the +fs input. the zero crossing occurs at the mid-scale input. 2. ideal density of 1s at modulator data output can be calculated with v in /640 mv + 50%; similarly, the adc code can be calculated with (v in /640 mv) 65,536 + 32,768, assuming a 16-bit unsigned decimation flter. acpl-7970 3-wire serial interface input current r shunt v in+ v in? v dd1 gnd1 isolated 5 v 0.1 f mclk mdat v dd2 gnd2 non- isolated 5 v/3.3 v 1 f sinc 3 filter clock data gnd v dd sclk sdat cs isolation barrier gnd1 gnd2 1 f 0.1 f digital filter a digital flter converts the single-bit data stream from the modulator into a multi-bit output word similar to the digital output of a conventional a/d converter. with this conversion, the data rate of the word output is also reduced (decimation). a sinc 3 flter is recommended to note: in applications, 1 m f/0.1 m f bypass capacitors are recommended to connect between pins v dd1 and gnd1, and between pins v dd2 and gnd2 of the acpl-7970. figure 17. typical application circuit with a sinc 3 flter. work together with the acpl-7970. with 256 decimation ratio and 16-bit word settings, the output data rate is 39 khz (= 10 mhz/256). this flter can be implemented in an asic, an fpga or a dsp. some of the adc codes with cor - responding input voltages are shown in table 5.
14 figure 18. typical application circuit with the hcpl-0872. acpl-7970 3-wire serial interface input current r shunt v in+ v in? v dd1 gnd1 isolated 5 v 0.1 f mclk mdat v dd2 gnd2 non- isolated 5 v 1 f hcpl-0872 mclk1 mdat1 gnd v dd sclk sdat cs isolation barrier gnd1 gnd2 1 f 0.1 f digital interface ic the hcpl-0872 digital interface ic (so-16 package) is a digital flter that converts the single-bit data stream from the modulator into 15-bit output words and provides a serial output interface that is compatible with spi ? , qspi ? , and microwire ? protocols, allowing direct connection to a microcontroller. instead of a digital flter implemented in software, the hcpl-0872 can be used together with the acpl-7970 to form an isolated programmable two-chip a/d converter. available in an so-16 surface-mount package, the digital interface ic has features include fve diferent conversion modes (combinations of speed and resolution), three diferent pre-trigger modes (allows conversion time < 1 m s), ofset calibration, fast over-range (over-current, or short circuits) detection, and adjustable threshold detection. figure 19. typical application circuit for motor phase current sensing. programmable features are confgured via the serial con - fguration port. a second multiplexed input is available to allow measurements with a second isolated modulator without additional hardware. refer to the hcpl-0872 data sheet for details. notes: spi and qspi are trademarks of motorola corp. microwire is a trademark of national semiconductor inc. application information digital current sensing circuit figure 19 shows a typical application circuit for motor control phase current sensing. by choosing the appro - priate shunt resistance, a wide range of current can be monitored, from less than 1 a to more than 100 a. acpl-7970 floating positive supply r sense v in + v in ? v dd1 gnd1 mclk mdat v dd2 gnd2 non- isolated 5 v/3.3 v isolation barrier gate drive circuit hv+ hv ? c1b 0.1 f d1 5.1 v c2 10 nf motor r2a 22 r1 r2b 22 + ? gnd2 c1a 1 f c3b 1 f c3a 0.1 f
15 power supplies and bypassing as shown in figure 19, a foating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 v using a simple zener diode (d1); the value of resistor r1 should be chosen to ensure sufcient current can be supplied from the existing foating supply. the voltage from the current sensing resistor or shunt (r sense ) is applied to the input of the acpl-7970 through an rc anti- aliasing flter (r2 and c2). and fnally, a clock is connected to the acpl-7970 and data are connected to the digital flter. although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. the power supply for the isolated modulator is most often obtained from the same supply used to power the power transistor gate drive circuit. if a dedicated supply is required, in many cases it is possible to add an additional winding on an existing transformer. otherwise, some sort of simple isolated supply can be used, such as a line powered trans - former or a high-frequency dc-dc converter. an inexpensive 78l05 three terminal regulator can also be used to reduce the foating supply voltage to 5 v. to help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass flter with the regulators input bypass capacitor. as shown in figure 19, bypass capacitors (c1a, c1b, c3a and c3b) should be located as close as possible to the input and output power-supply pins of the isolated modulator. the bypass capacitors are required because of the high-speed digital nature of the signals inside the isolated modulator. a bypass capacitor (c2) is also recom - mended at the input due to the switched-capacitor nature of the input circuit. the input bypass capacitor also forms part of the anti-aliasing flter, which is recommended to prevent high frequency noise from aliasing down to lower frequencies and interfering with the input signal. pc board layout the design of the printed circuit board (pcb) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. in addition, the layout of the pcb can also afect the isolation transient immunity (cmr) of the isolated modulator, due primarily to stray capacitive coupling between the input and the output circuits. to obtain optimal cmr perfor - mance, the layout of the pc board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the pc board does not pass directly below or extend much wider than the body of the isolated modulator. shunt resistors the current-sensing shunt resistor should have low re - sistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely afect operation), and reasonable tolerance (to maintain overall circuit accuracy). choosing a particu - lar value for the shunt is usually a compromise between minimizing power dissipation and maximizing accuracy. smaller shunt resistances decrease power dissipation, while larger shunt resistances can improve circuit accuracy by utilizing the full input range of the isolated modulator. the frst step in selecting a shunt is determining how much current the shunt will be sensing. the graph in figure 20 shows the rms current in each phase of a three- phase induction motor as a function of average motor output power (in horsepower, hp) and motor drive supply voltage. the maximum value of the shunt is determined by the current being measured and the maximum recom- mended input voltage of the isolated modulator. the maximum shunt resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the shunt should see during normal operation. for example, if a motor will have a maximum rms current of 10 a and can experience up to 50% overloads during normal operation, then the peak current is 21.1 a (= 10 x 1.414 x 1.5). assuming a maximum input voltage of 200 mv, the maximum value of shunt resistance in this case would be about 10 m . the maximum average power dissipation in the shunt can also be easily calculated by multiplying the shunt re - sistance times the square of the maximum rms current, which is about 1 w in the previous example. figure 20. motor output horsepower vs. motor phase current and supply. motor phase current - a (rms) 15 40 0 35 25 10 30 20 5 5 35 30 0 20 25 15 10 motor output power - horsepower 440 v 380 v 220 v 120 v
16 if the power dissipation in the shunt is too high, the resis - tance of the shunt can be decreased below the maximum value to decrease power dissipation. the minimum value of the shunt is limited by precision and accuracy require - ments of the design. as the shunt value is reduced, the output voltage across the shunt is also reduced, which means that the ofset and noise, which are fxed, become a larger percentage of the signal amplitude. the selected value of the shunt will fall somewhere between the minimum and maximum values, depending on the par - ticular requirements of a specifc design. when sensing currents large enough to cause signif - cant heating of the shunt, the temperature coefcient (tempco) of the shunt can introduce nonlinearity due to the signal dependent temperature rise of the shunt. the efect increases as the shunt-to-ambient thermal resis - tance increases. this efect can be minimized either by reducing the thermal resistance of the shunt or by using a shunt with a lower tempco. lowering the thermal resis - tance can be accomplished by repositioning the shunt on the pc board, by using larger pc board traces to carry away more heat, or by using a heat sink. for a two-terminal shunt, as the value of shunt resistance decreases, the resistance of the leads becomes a signif - cant percentage of the total shunt resistance. this has two primary efects on shunt accuracy. first, the efective resis - tance of the shunt can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the lead during assembly (these issues will be discussed in more detail shortly). second, the leads are typically made from a material such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco for the shunt overall. both of these efects are eliminated when a four-terminal shunt is used. a four-terminal shunt has two additional terminals that are kelvin-connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. because of the kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. several four-terminal shunts from isotek (isabellenhtte) suitable for sensing currents in motor drives up to 71 arms (71 hp or 53 kw) are shown in table 11; the maximum current and motor power range for each of the pbv series shunts are indicated. for shunt resistances from 50 m down to 10 m , the maximum current is limited by the input voltage range of the isolated modulator. for the 5 m and 2 m shunts, a heat sink may be required due to the increased power dissipation at higher currents. when laying out a pc board for the shunts, a couple of points should be kept in mind. the kelvin connections to the shunt should be brought together under the body of the shunt and then run very close to each other to the input of the isolated modulator; this minimizes the loop area of the connection and reduces the possibility of stray magnetic felds from interfering with the measured signal. if the shunt is not located on the same pc board as the isolated modulator circuit, a tightly twisted pair of wires can accomplish the same thing. also, multiple layers of the pc board can be used to increase current carrying capacity. numerous plated-through vias should surround each non-kelvin terminal of the shunt to help distribute the current between the layers of the pc board. the pc board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 a. making the current carrying traces on the pc board fairly large can also improve the shunts power dissipa - tion capability by acting as a heat sink. liberal use of vias where the load current enters and exits the pc board is also recommended. table 11. isotek (isabellenhtte) four-terminal shunt summary. shunt resistor part number shunt resistance tol. maximum rms current motor power range 120 v ac C 440 v ac m % a hp kw pbv-r050-0.5 50 0.5 3 0.8-3 0.6-2 pbv-r020-0.5 20 0.5 7 2-7 1.4-5 pbv-r010-0.5 10 0.5 14 4-14 3-10 pbv-r005-0.5 5 0.5 25 (28) 7-25 (8-28) 5-19 (6-21) pbv-r002-0.5 2 0.5 39 (71) 11-39 (19-71) 8-29 (14-53) note: values in brackets are a heatsink for the shunt.
17 shunt connections the recommended method for connecting the isolated modulator to the shunt resistor is shown in figure 19. v in + of the acpl-7970 is connected to the positive terminal of the shunt resistor, while v in C is shorted to gnd1, with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. this allows a single pair of wires or pc board traces to connect the isolated modulator circuit to the shunt resistor. by referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the shunt are seen as a common-mode signal and will not interfere with the current-sense signal. this is important because the large load currents fowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and ofsets that are relatively large compared to the small voltages that are being measured across the current shunt. if the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very important that the connection from gnd1 of the isolated modulator to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. the only direct connec - tion between the isolated modulator circuit and the gate drive circuit should be the positive power supply line. in some applications, however, supply currents fowing through the power-supply return path may cause ofset or noise problems. in this case, better performance may be obtained by connecting v in + and v in C directly across the shunt resistor with two conductors, and connecting gnd1 to the shunt resistor with a third conductor for the power-supply return path, as shown in figure 21. when connected this way, both input pins should be bypassed. to minimize electromagnetic interference of the sense signal, all of the conductors (whether two or three are used) connecting the isolated modulator to the sense resistor should be either twisted pair wire or closely spaced traces on a pc board. the resistor r2 in series with the input lead forms a low pass anti-aliasing flter with the input bypass capacitor c2. the resistor performs another important function as well; it dampens any ringing which might be present in the circuit formed by the shunt, the input bypass capacitor, and the inductance of wires or traces connect - ing the two. undamped ringing of the input circuit near the input sampling frequency can alias into the baseband producing what might appear to be noise at the output of the device. figure 21. schematic for three conductor shunt connection. acpl-7970 floating positive supply r sense v in + v in ? v dd1 gnd1 mclk mdat v dd2 gnd2 non- isolated 5 v/3.3 v isolation barrier gate drive circuit hv+ hv ? c1b 0.1 f d1 5.1 v c2a 20 nf motor r2a 22 r1 r2b 22 + ? gnd2 c1a 1 f c3b 1 f c3a 0.1 f c2b 20 nf
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. av02-2856en - november 29, 2012 voltage sensing the acpl-7970 can also be used to isolate signals with amplitudes larger than its recommended input range with the use of a resistive voltage divider at its input. the only restrictions are that the impedance of the divider be relatively small (less than 1 k ) so that the input resistance (24 k ) and input bias current (0.3 m a) do not afect the accuracy of the measurement. an input bypass capacitor is still required, although the damping resistor is not (the resistance of the voltage divider provides the same function). the low-pass flter formed by the divider resis - tance and the input bypass capacitor may limit the achiev - able bandwidth. to obtain higher bandwidth, the input bypass capacitor (c2) can be reduced, but it should not be reduced much below 1000 pf to maintain adequate input bypassing of the isolated modulator.

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